The present invention relates to a cache storage apparatus of information processing apparatus. More particularly, the invention concerns a cache storage apparatus wherein the frequency of access by one of a plurality of access requestors to the cache directory unit can be reduced so that possibility of access by another requestor to the cache directory unit can be made high to thereby improve the utilization coefficient of the apparatus.
A cache storage apparatus is constructed of a cache storage unit for storing data of a main storage in units of several areas (hereinafter called line unit), and a cache directory unit for storing main storage addresses (line addresses) of the data stored in the cache storage unit. When a memory request is issued from a requestor, the cache directory unit is searched. The cache storage unit is then accessed in accordance with the search result.
There is known a method of improving the utilization coefficient of a cache storage apparatus of this type, as disclosed for example in Japanese Patent Laid-open Publication NO. JP-A-61-80447. According to this method, for example, two consecutive 8 byte store instructions at the same line address are merged into one 16 byte store instruction within a stack of the cache storage apparatus when the addresses thereof are succeeding. Therefore, the cache directory unit is searched only once instead of two times in order to access the cache storage unit, and the frequency of access to the cache directory unit can be reduced to allow the resultant vacant time to be used for processing another request. With this method, however, the reduction of frequency of access to the directory unit can be made only when store instructions from one requestor are consecutively sent and the addresses of the two succeeding store instructions are succeeding, and cannot be expected in other cases. Therefore, the advantage of such reduction is substantially limited.
Another method of improving the utilization coefficient of a cache storage apparatus is disclosed, e.g., in Japanese Patent Laid-open Publication No. JP-A-54-66727 wherein the directory unit is divided into a plurality of banks to allow concurrent processing of access requests from a plurality of requestors. Although this method has many advantageous points from the view point of utilization coefficient of a cache storage apparatus, the quantity of hardwares for controlling and addressing a plurality of banks is expected to increase, resulting in expensive cost.